This invention relates generally to lead frames for use in packaged integrated circuits. More particularly it relates to lead frames designs that incorporate electrostatic discharge protection to reduce the likelihood of integrated circuit burnout in the event of an electrostatic discharge.
It is well known that the unavoidable and naturally occurring phenomenon of electrostatic discharge can induce very high currents and voltage surges, which may exceed many thousands of volts. In the absence of any integrated circuit protection device, the current surge or overvoltage may penetrate an integrated circuit and cause hardware damage such as integrated circuit burnout or electronic malfunction, e.g. memory loss or loss of transmission data. Integrated circuits that are manufactured using the Metal Oxide Semiconductor (MOS) or similar technology may be considered, as an example of integrated circuits that may be rendered inoperable by electrostatic discharge. As is well known to those of skill in the art, Metal Oxide Semiconductor (MOS) devices generally employ a gate structure, which includes an insulative thin film layer typically formed from silicon dioxide. Under overvoltage conditions that may be attributed to electrostatic discharge, the thin film gate insulative layer may suffer from dielectric breakdown of potentials, for example, around 10 volts for a 0.35 micron process whereby the gate is shorted and the entire device is rendered inoperable. As the integrated circuit fabrication technology moves to smaller feature sizes designed to operate under lower current densities, the energy necessary to cause such damage is reduced even further.
In an effort to protect integrated circuits against overvoltage in general and by electrostatic discharge in particular, manufacturers have incorporated a variety of circuit protection devices into chip designs. By way of example, one prior art integrated circuit package design that incorporates a circuit protection device is disclosed by U.S. Pat. No. 4,928,199 to Diaz et al. In this design, an integrated circuit package includes a die that is protected by a metallic cavity cover, which is connected to ground voltage and functions as ground plane. The circuit protection device, e.g. a glass layer, is placed on an interior surface of the cavity cover such that it contacts bonding wires, which connect bond pads on the die to leads on a lead frame.
Under normal operating conditions, the circuit protection device has high resistance. In response to a short voltage surge, however, the circuit protection device in a relatively short period of time is transformed from its high resistance state to a low resistance state. Soon after the short voltage surge comes to an end, the circuit protection device reverts back to its original high resistance state.
In the prior art integrated circuit package design mentioned above, a voltage surge generated from external circuitry entering into the integrated circuit package passes through the bonding wires, which are in contact with the circuit protection device. In response to the voltage surge, the circuit protection device transforms itself from a high resistance state to a low resistance state and conducts the voltage surge to the ground plane cavity cover. In this manner, the circuit protection device protects the die from a burnout that may result from a voltage surge generated at external circuitry. Although this design protects the die from voltage surges, it suffers from several drawbacks. Accordingly,-improved integrated circuit package designs that provide adequate electrostatic discharge protection utilizing an efficient process for manufacturing such a package design would be desirable.